This invention relates generally to semiconductor devices and specifically to a method of forming a memory cell with an alternate self-aligned contact implementation.
As DRAMS increase in memory cell density, there is a continuous challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One way of increasing cell capacitance is to through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors.
To increase feature density and thus decrease memory cell size, Self Aligned Contacts (SAC) have been employed. The self aligned nature is accomplished by definition (patterning and etching) of a contact whose electrical contact (active) area is defined by pre-existing features and not the patterned contact area. Even when utilizing self aligned processes, the feature size is sufficiently small that complex photolithography processes (e.g., phase shifted reticules) are required for patterning and alignment is critical.
In some processes for forming DRAM devices, the active contact area is defined by removing (etching) the contact oxide defined by the pattern (mask) and is self-aligned to some particular structures (e.g., the transfer gate and field oxide region). To provide insulation and selectivity for the contact oxide to the self align structures an alternate dielectric material (e.g., silicon nitride=SiN4) is used to encapsulate the transfer gate. The dielectric exists on the top (defined at the previous gate patterning operation) and sides ) formed at the previous sidewall formation) of the transfer gate. The active device area (moat), a silicon region, is defined by the isolation oxide (field oxide). The implementation of this technique utilizes differences in etch rates of dissimilar materials (etch selectivity) to provide final film thickness and over-etch process margin.
The utilization of the silicon nitride to encapsulate the transfer gate sidewall material increases the parasitic capacitance to adjacent conductor lines due to the high dielectric constant of the material. This type of approach has high process complexity and low process margin. Both problems are the result of the small contact size and inadequate selectivity (ratio of silicon dioxide etch rate to silicon nitride etch rate) during silicon dioxide etching of the contact with the available etch technology (tools and processes).
The present invention provides a method of forming a memory cell with a new approach for self-aligned contacts, which overcomes many of the problems exhibited by the prior art. For example, the present invention decreases process complexity, decreases parasitic capacitance to adjacent electrical conductors (e.g., DRAM word line), increases patterning process margin and increases etching process margin by utilizing fewer process steps, lower dielectric constant materials, relaxing minimum feature size at the contact patterning and by elimination of the need for high silicon dioxide (SiO2) to silicon nitride (SiN4) selectively at contact etching. Aspects of the invention will have specific application in 64 Meg and larger DRAM process flows and beyond.
The present invention implements self aligned electrical connections without hole (contact) pattern definition. Planar conductive (polysilicon) and insulating (silicon dioxide and silicon nitride) films are used to enable the use of high selectivity etch processes for stacked memory structure cell definition.
In one embodiment, the present invention provides a method of forming a dynamic random access memory device, which utilizes self-aligned contact pads for the bit line and storage node contacts. A transfer gate is formed at the face of a semiconductor region. The semiconductor region includes a bit line contact region and a storage node contact region at opposite edges of the transfer gate. The transfer gate is surrounded with an insulating material, preferably silicon dioxide. A conductive layer is formed over the transfer gate, over the bit line contact region and over the storage node contact region. This conductive layer is then etched so that a first portion of the conductive layer provides an electrical contact to the bit line contact region and a second portion of the conductive layer provides an electrical contract to the storage node contact region. The bit line and storage nodes can then be formed in electrical contact with the first and second portions of the conductive layer, respectively.
Concentrating on another aspect of the present invention, first and second transfer gates are formed at the face of a semiconductor region. The semiconductor region includes a bit line contact region located between the first an second transfer gates. As before, the transfer gate is surrounded with an insulating material such as silicon dioxide.
A conductive layer, preferably polysilicon, is formed over the transfer gate, over the bit line contact region and over the storage node contact region. A masking layer, preferably silicon dioxide, is then formed over the conductive layer. A contact window is then formed by removing a portion of the masking layer so as to expose a portion of the conductive layer over the bit line contact regions and over portions of the first and second transfer gates which are adjacent to the bit line contract region.
A bit line layer(s) can then be formed over the masking layer and the exposed portion of the conductive layer. A bit line can then be formed by patterning and etching the bit line layer. This patterning and etching step also exposes a portion of the conductive layer between the masking layer and the bit line. The exposed portion of the conductive layer can then be removed using the masking layer as a mask. A storage node electrode can then be formed in electrical contact with a portion of the conductive layer, which overlies the storage node contact region.
The method of the present invention can be used to fabricate a novel memory device. This device includes at least one transfer gate formed in an active region of a semiconductor device. The transfer gate is spaced from a field oxide region by a contact region within the active region. A top surface insulator is disposed along the top surface of the transfer gate and is formed from a first material (e.g., an oxide). A sidewall insulator is disposed along the sidewall of the transfer gate and is formed from a second material (e.g., an oxide). A conductive pad (e.g., polysilicon) extends from over a portion of the field oxide region to over a portion of the top surface insulator. This conductive pad abuts the contact region of the active area. A storage node conductor, which serves as one plate of a capacitor, abuts the conductive pad.
In another aspect, a novel memory device includes first and second transfer gates. Both gates have a top surface insulator and a sidewall insulator. The top surface insulator a sidewall insulator are formed from different materials. A conductive pad extends over a portion of the first top surface insulator, the first sidewall insulator, the contact region within the active area, the second sidewall insulator, and a portion of the second top surface insulator. The conductive pad abuts the contact region of the active area. A bit line conductor comprises a bit line within a memory array.
The present invention has a number of advantages over prior art processes. First, process complexity is reduced by the elimination of two etches, two polysilicon depositions, one silicon dioxide deposition and one silicon nitride deposition as compared with other processes. In addition, the contact etch margin is improved by the elimination of special high selectivity processes. Only industry standard etch processes are required to implement the poly pad self aligned contact process. The industry standard interconnect contact etch process selectivity is sufficient to provide over etch margin.
This processing approach also reduces word line (transfer gate) parasitic capacitance by utilization of silicon dioxide rather than silicon nitride as the masking and sidewall material.
Fourth, this processing approach provides an opportunity to improve the average and standard deviation of the DRAM device pause by elimination of one of the known causes of pause degradation. The process also provides an opportunity to perform special pause improvement process steps prior to sealing the single crystal silicon (moat) regions. Pause degradation is known to be due to silicon lattice damage and other lattice disruption. Since no contact etching comes in contact with the moat regions the normal degradation due to this process is eliminated.
Using the preferred embodiment of the present invention, oversized bit line contacts and undersized bit line are used. These elements in the contact region are sized for the proven production device design (layout) and Design Registration Accuracy (DRA) capability inherent in the present pattern and etch tool set. With an alternate layout the cell size can be decreased with the current DRA capability. As the DRA capability is improved the cell size can be decreased.
It should also be noted that no changes to the standard ion implantation strategy are needed. All diffused regions are defined prior to the application of the polysilicon pad. Finally, since the polysilicon pad is applied after all ion implantation processes, the moat sealing and polysilicon landing pad formation can be integrated into the periphery circuit processing without other process modifications. The polysilicon pad is a satisfactory structure for interconnect contact connection after the cell processing.
The example embodiment of the new SAC structure uses a 2 transistor cell with common active region (Bit line contact) a separate storage node contacts. This invention can be equally implemented in a single transistor structure.